Mc68Vz328 User's Manual; Page-Hit Sdram Cpu Read Cycle (Cas Latency = 1); Figure 19-16 Page-Hit Sdram Cpu Read Cycle Timing Diagram - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
19.3.15

Page-Hit SDRAM CPU Read Cycle (CAS Latency = 1)

Figure 19-16 shows the timing diagram for the page-hit SDRAM CPU read cycle. The signal values and
units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about the
operation of individual signals can be found in both Chapter 8, "LCD Controller," and Chapter 7, "DRAM
Controller."
S0
SDCLK
SCKEN
A[16:1]/MD[15:0]
SDA10
CS
RAS
CAS
D[15:0]
WE
DQM
DTACK
Figure 19-16. Page-Hit SDRAM CPU Read Cycle Timing Diagram
19-20
S1 S2 S3 S4 S4 S4
Col
6
Read
Command

MC68VZ328 User's Manual

S5 S6 S7