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PGSEL
BIT 7
TYPE
RESET
Name
Reserved
Reserved
Bits 7–6
SELx
Select—These bits select whether the internal chip
Bits 5–0
function or I/O port signals are connected to the pins.
10.4.9
Port J Registers
Port J is composed of the following four general-purpose I/O registers:
•
Port J direction register (PJDIR)
•
Port J data register (PJDATA)
•
Port J pull-up enable register (PJPUEN)
•
Port J select register (PJSEL)
Each signal in the PJDATA register connects to an external pin. As on the other ports, each bit on Port J is
individually configured.
10.4.9.1
Port J Direction Register
The direction register controls the direction (input or output) of the line associated with the PJDATA bit
position. When the data bit is assigned to a dedicated I/O function by the PJSEL register, the DIR bits are
ignored. The settings for the bit positions are shown in Table 10-41.
PJDIR
BIT 7
DIR7
TYPE
rw
0
RESET
Name
DIRx
Direction—These bits control the direction of the pins in
Bits 7–0
an 8-bit system. They reset to 0.
Port G Select Register
6
5
SEL5
rw
0
0
0
Table 10-40. Port G Select Register Description
Description
Port J Direction Register
6
5
DIR6
DIR5
rw
rw
0
0
Table 10-41. Port J Direction Register Description
Description
I/O Ports
4
3
SEL4
SEL3
SEL2
rw
rw
rw
0
1
0x08
These bits are reserved and should be set to 0.
0 = The dedicated function pins are connected.
1 = The I/O port function pins are connected.
4
3
2
DIR4
DIR3
DIR2
rw
rw
rw
0
0
0
0x00
0 = Input
1 = Output
Programming Model
0x(FF)FFF433
2
1
BIT 0
SEL1
SEL0
rw
rw
0
0
0
Setting
0x(FF)FFF438
1
BIT 0
DIR1
DIR0
rw
rw
0
0
Setting
10-31
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