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Programming Model
10.4.7
Port F Registers
Port F is composed of the following 8-bit general-purpose I/O registers:
•
Port F direction register (PFDIR)
•
Port F data register (PFDATA)
•
Port F pull-up enable register (PFPUEN)
•
Port F select register (PFSEL)
Each signal in the PFDATA register connects to an external pin. As on the other ports, each bit on Port F is
individually configured.
10.4.7.1
Port F Direction Register
The Port F direction register controls the direction (input or output) of the line associated with the
PFDATA bit position. When the data bit is assigned to a dedicated I/O function by the PFSEL register, the
DIR bits are ignored. The settings for the PFDIR bit positions are shown in Table 10-31.
PFDIR
BIT 7
DIR7
TYPE
rw
0
RESET
Name
DIRx
Direction—These bits control the direction of the pins in an 8-bit
Bits 7–0
system. They reset to 0.
10-24
Port F Direction Register
6
5
DIR6
DIR5
rw
rw
0
0
Table 10-31. Port F Direction Register Description
Description
MC68VZ328 User's Manual
4
3
2
DIR4
DIR3
DIR2
rw
rw
rw
0
0
0
0x00
0 = Input
1 = Output
0x(FF)FFF428
1
BIT 0
DIR1
DIR0
rw
rw
0
0
Setting
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