Table 4-3 Wksel Field (Pllcr) Delay Settings - Motorola MC68VZ328 User Manual

Table 4-2. PLL Control Register Description (Continued)
Name
DISPLL Disable PLL—This bit, when set, disables the
Bit 3 output of the PLL, placing the chip in sleep
mode, its lowest power state.
Reserved Reserved
Bit 2
WKSEL Wake-up Clock Select—This field selects the
Bits 1–0 delay of the PLL output from the initiation of
the wake up until an output is available. Since
the delay time is calculated by counting CLK32
cycles, the frequency of the crystal oscillator
will determine the amount of delay that each
setting produces.
Bits 1–0 CLK32 Periods
00
01
10
11
Clock Generation Module and Power Control Module
Description
Table 4-3. WKSEL Field (PLLCR) Delay Settings
Delay in Milliseconds
(32.768 kHz)
32
48
64
96 2.93 (default)
0 = PLL enabled (default).
1 = PLL disabled.
This bit is reserved and should be set to 0.
See Table 4-3 for delay settings.
Delay in Milliseconds
0.976
1.465
1.953
2.500 (default)
CGM Programming Model
Setting
(38.4 kHz)
0.833
1.250
1.667
4-9