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Preparation for Use
2.10 MULTIBUS BUS ACCESS
The iSBC 432/ 100 board contains no local memory.
All system memory resides on separate Multibus
modules. Both system memory and all 1/0 ports
(including 1/0 ports contained on the processor
board) must be accessed via the Multibus bus. Each
GDP access specifies either a local address or a
physical address (refer to the discussion in Chapter
3). Local address requests are translated into
Multibus 1/0 commands; physical address requests
are translated into Multibus memory commands.
The iSBC 432/ 100 board is designed to operate with
either 8-bit or 16-bit memory modules. A user-
selectable jumper (table 2-2) is provided to select the
8-bit or 16-bit Multibus transfer mode. (The board is
factory-configured to operate in the 8-bit mode.)
GDP memory accesses may require the transfer of
one to ten data bytes over the Multibus bus. In the 8-
bit mode, all GDP memory requests initiate a series
of single-byte read or write accesses. In the 16-bit
mode, all GDP multibyte memory requests that
originate on even byte boundaries are satisfied by a
series of double-byte (16-bit) read or write accesses.
All other accesses are performed in the same manner
as are accesses in the 8-bit mode.
When operating with iSBC/MDS* 016 16K
RAM memory modules, the 8-bit mode must
be used. The 16-bit mode may be used with
iSBC/MDS 032/048/064 RAM memory
modules.
As mentioned earlier, a single GDP memory request
may require the transfer of ten data bytes over the
Multibus bus. In order to shorten the overall time
required for these data transfers, the bus may be
locked from the beginning of the first transfer until
the GDP memory transfer has been completed.
Locking the bus eliminates the time required to·
acquire and release the bus for each byte data
transfer. This "bus lock" feature, which results in
higher processor throughput, is user selectable as
described in table 2-2. The processor board is shipped
with the "bus lock" feature enabled.
The bus lock provision cannot be enabled in
systems
with
double-density
diskette
controllers and 8-bit memory if the diskette
controller will operate simultaneously with
· the iSBC 432/100 board.
*"lllDS"
is an ordering code only, and is not used as a
product name or trademark.
MOS® is a registered
trademark of Mohawk Data Sciences Corp.
2-4
iSBC 432/100
2.11 MULTIBUS BUS CONFIGURATION
For system applications, the iSBC 432/ 100 board is
designed for installation in a standard Multibus
backplane (e.g., an Intellec Microcomputer Develop-
ment System). Multibus signal characteristics and
methods of implementing a serial or parallel priority
resolution scheme for resolving bus contention in a
multiple bus master system are described in the
following paragraphs.
Always turn off the system power supply
before installing or removing any board
from the backplane. Failure to observe this
precaution can cause damage to the board.
2.12 SIGNAL CHARACTERISTICS
As shown in figure 1-1, connector P 1 interfaces the
iSBC 432/100 board to the Multibus bus. The pin
assignments for this 86-pin connector are listed in
table 2-3 and descriptions of the signal functions are
provided in table 2-4.
The de characteristics of the iSBC 432/ 100 bus inter-
face are provided in table 2-5. The ac characteristics
of the iSBC 432/ 100 board when operating in the
master mode and slave mode are provided in tables
2-6 and 2-7, respectively. Bus exchange timing
diagrams are provided in figures 2-1 and 2-2.
2.13 SERIAL PRIORITY RESOLUTION
In a multiple bus master system, bus contention can
be resolved by implementing a serial priority resolu-
tion scheme as shown in figure 2-3. Due to the prop-
agation delay of the BPRO/ signal path, this scheme
is limited to a maximum of three bus masters capable
of acquiring and controlling the Multibus bus. In the
configuration shown in figure 2-3, the bus master
installed in slot J2 has the highest priority and is able
to acquire control of the bus at any time because its
BPRN/ input is always enabled (tied to ground).
If the bus master in slot J2 desires control of the
Multibus bus, it drives its BPRO/ output high and
inhibits the BPRN/ input to all lower-priority bus
masters. When finished using the bus, the J2 bus
master pulls its BPRO/ output low and gives the J3
bus master the opportunity to take control of the
bus. If the J3 bus master does not desire to control
the bus at this time, it pulls its BPRO/ output low
and gives the lowest priority bus master in slot J4 the
opportunity to assume control of the bus.
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