System Bus Reset And Configuration Timings (For The S.e.p. And Ppga Packages); System Bus Reset And Configuration Timings (For The Fc-Pga/Fc-Pga2 Package) - Intel CELERON 1.10 GHZ Datasheet

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Intel Celeron Processor up to 1.10 GHz
Figure 6. System Bus Reset and Configuration Timings (For the S.E.P. and PPGA Packages)
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
Figure 7. System Bus Reset and Configuration Timings (For the FC-PGA/FC-PGA2 Package)
Configuration
(A20M#, IGNNE#,
LINT[1:0])
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
50
BCLK
RESET#
T = T9 (AGTL+ Input Hold Time)
t
T = T8 (AGTL+ Input Setup Time)
u
T = T10 (RESET# Pulse Width)
v
T = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
w
T = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
x
BCLK
RESET#
T
y
T = T9 (AGTL+ Input Hold Time)
t
T = T8 (AGTL+ Input Setup Time)
u
T = T10 (RESET# Pulse Width)
v
T = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
w
T = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
x
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)
Tz = T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
T
v
T
w
Valid
T
v
T
z
Safe Valid
T
w
T
u
T
t
T
x
T
u
T
t
T
x
Valid
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