Single Dram Interface: Write; Figure 4.17-30 Example Of Single Dram Interface Write Timing Chart - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 4 BUS INTERFACE

4.17.15 Single DRAM Interface: Write

This section provides a single DRAM interface write timing chart.
Single DRAM Interface: Write Timing Chart
Bus width: 16 bits, access: words

Figure 4.17-30 Example of Single DRAM Interface Write Timing Chart

Q1
CLK
2)2CAS/1WE
A24-00 X
D31-24 W
D23-16 W
RAS
CASL
CASH
WE
RDX
(DACK0)
(EOP0)
[Explanation of operation]
• Column addresses and write data are output in Q4SW cycles.
• CAS is asserted at the falling edge of Q4SW and negated at the rising edge or end of the
Q4SW cycle.
• WE (including WEL and WEH) is asserted at the rising edge of the Q4SW cycle and negated
when Q4SW ends.
186
Q2 Q3 Q4SW
row.adr. col. col.
W
W
High speed
page
Q4SW Q4SW Q4SW
col. col.
W W
W W
High speed High speed
page page
Q1 Q2 Q3
X row.adr. col.
W
W
Q4SW