4.18 Internal Clock Multiplication (Clock Doubler)
Figure 4.18-2 Example of Timing for 1X Clock (BW-16bit, Access-Word Read)
Internal clock
Internal instruction
N
N + 2
address
Internal instruction
D
D + 2
data
CLK output
External address bus
N
N + 4
D + 2
External data bus
D
D + 2
External RDX
External fetch (instruction fetch)
Prefetch
195