Branch Instructions With Delay Slots - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 2 CPU
2.7.1

Branch Instructions with Delay Slots

A branch instruction causes the program to branch and execute the instruction at the
branch destination after the instruction (called the delay slot) placed immediately after
the branch instruction is executed.
Branch Instructions with Delay Slots
The following instructions execute branch operation with a delay slot:
JMP:D
BRA:D
BC:D
BV:D
BLE:D
Theory of Operation of Branch Instructions with Delay Slots
A branch instruction causes the program to branch and execute the instruction at the branch
destination after the instruction (called the delay slot) placed immediately after the branch
instruction is executed.
Since a delay slot instruction is executed before branching, the execution speed seems one
cycle. However, when a valid instruction cannot be put at the delay slot, the NOP instruction
must be provided.
[Example]
;
LABEL :
For a conditional branch instruction, the instruction placed at the delay slot is executed whether
the branch condition is satisfied or not.
For delayed branch instructions, the execution order of some instructions seems to be reversed.
This is only applicable to PC updating.
referencing, are executed in order of coding.
Concrete examples are shown below.
48
@Ri CALL:D
label9 BNO:D
label9 BNC:D
label9 BNV:D
label9 BGT:D
Instruction list
ADD R1, R2
BRA:D LABEL
MOV R2, R3
:
ST R3, @R4
label12 CALL:D
label9 BEQ:D
label9 BN:D
label9 BLT:D
label9 BLS:D
;
; Branch instruction
; Delayed slot---Executed before branching
; Branch destination
Other operations, such as register updating and
@Ri RET:D
label9 BNE:D
label9 BP:D
label9 BGE:D
label9 BHI:D
label9
label9
label9
label9