Gear Function; Figure 3.9-1 Gear Controller Block Diagram - Fujitsu MB91F109 FR30 Hardware Manual

3.9

Gear Function

The gear function supplies clock pulses by slowing down the clock pulse intervals.
The function uses two independent circuits for the CPU and peripherals. Data can be
transferred between the CPU and peripherals even when both circuits use different
gear ratios. The function also permits a source clock to be selected from two choices.
One is the clock having the same cycle as the clock from PLL and one is the clock that
has passed through a divide-by-two frequency circuit.
Gear Controller Block Diagram
Figure 3.9.1 is a block diagram of the gear controller.
Internal bus
Oscilla-
X0
tion
X1
circuit
PLL
Gear Function Setting
The desired gear ratio for CPU clock control can be set by setting the CCK1 and CCK0 bits of
the gear control register (GCR) to the desired values. Similarly, the desired gear ratio for
peripheral clock control can be set by setting the PCK1 and PCK0 bits of the same register to
the desired values.

Figure 3.9-1 Gear Controller Block Diagram

GCR
CCK
CPU clock
gear interval
PCK
generation circuit
DBLON
CHC
Peripheral clock
gear interval
generation circuit
1/2
Source clock
CPU clock gear interval
indication signal
Peripheral clock gear interval
indication signal
3.9 Gear Function
CPU clock
Internal bus clock
Internal DMA clock
External bus clock
Internal peripheral clock
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