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CHAPTER 3 CLOCK GENERATOR AND CONTROLLER
3.10 Standby Mode (Low Power Consumption Mechanism)
The standby mode implies the stop state and sleep state.
Outline of Stop State
In the stop state, all internal clocks and the operation of the oscillation circuit are stopped so as
to minimize power consumption.
Proceed as follows to shift to the stop state:
•
Using an instruction to write to the standby control register (STCR)
Perform one of the following to return to the operating state:
•
Interrupt request (limited to the peripherals that permit an interrupt request to occur even in
the stop state)
•
Applying the L level to the RSTX pin
Since all internal clocks are stopped in the stop state, internal peripherals other than those that
cause an interrupt to return remain stopped.
Outline of Sleep State
In the sleep state, the CPU clock and internal bus clock are stopped. Power consumption when
CPU operation is not required can be suppressed to a certain degree.
Proceed as follows to transit to the sleep state:
•
Using an instruction to write to the standby control register (STCR)
Perform one of the following to to return to the operating state:
•
Interrupt request
•
Issue a reset cause
Since the internal DMA clock and peripheral clock operate in the sleep state, the sleep state can
be canceled by causing an interrupt from any of the internal peripherals that use one of the two
clock sources.
Types of Operation in Standby Mode
Table 3.10.1 lists the types of operations performed in standby mode.
Table 3.10-1 Types of Operation in Standby Mode
Operating
Transition
status
condition
Run
Sleep
STCR
SLEP = 1
Stop
STCR
STOP = 1
Y: Operating X: Stopped
90
Oscillator
Internal clock
CPU/
internal bus
Y
Y
Y
X
X
X
Peripheral
DMA/
peripheral
Y
Y
Y
Y
X
X
Pin
Cancel
method
Active
Active
*
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