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<Note>
Seven-bit data can be used only in normal mode (mode 0) for asynchronous (start-stop)
communication. Use eight-bit data in multiprocessor mode (mode 1) or CLK synchronous
communication mode (mode 2).
[bit 3] A/D (Address/Data)
This bit specifies the data format of frames that are transmitted in multiprocessor mode
(mode 1) for asynchronous (start-stop) communication.
0: Data frame (Initial value)
1: Address frame
[bit 2] REC (Receive Error Clear)
Setting this bit to "0" clears the error flags (PE, ORE, and FRE) of the SSR register.
Operations for setting this bit to "1" are invalid. The value read from the bit is always "1".
[bit 1] RXE (Receiver Enable)
This bit controls UART receive operation.
0: Disable UART receive operation. (Initial value)
1: Enable UART receive operation.
<Note>
If the UART receive operation is disabled during reception processing (while data is input to the
reception shift register), the receive operation is stopped when the reception of the current
frame is completed and the received data is stored in the receive data buffer SIDR register.
[bit 0] TXE (Transmitter Enable)
This bit controls UART transmit operation.
0: Disable UART transmit operation. (Initial value)
1: Enable UART transmit operation.
<Note>
If the UART transmit operation is disabled during transmission processing (while data is output
from the transmit register), the transmit operation is stopped when no data is left in the
transmission data buffer SODR register.
10.3 Serial Control Register (SCR)
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