Fujitsu MB91F109 FR30 Hardware Manual page 450

INDEX
Index
Numerics
0-detection ........................................................... 295
16/31-bit immediate value transfer or immediate
value setting ............................................... 413
16/8-bit data, data transfer block for .................... 345
16-bit bus width ............................ 142, 144, 149, 150
16-bit data bus ..................................................... 157
16-bit reload register (TMRLR)............................. 286
16-bit reload time register .................................... 282
16-bit reload timer block diagram .........................283
16-bit timer register (TMR) ................................... 286
1-detection ........................................................... 295
1-detection data register (BSD1).......................... 293
20-bit delayed-branch macro instruction .............. 419
20-bit standard branch macro instruction............. 418
32 bits - 16 bits bus converter ................................ 32
32-bit architecture .................................................. 30
32-bit delayed-branch macro instruction .............. 421
32-bit standard branch macro instruction............. 420
8-bit bus width .............................. 143, 145, 149, 150
8-bit data bus ....................................................... 156
A
A/D converter block diagram................................ 269
A/D converter operation mode ............................. 276
A/D converter register .......................................... 268
A/D converter, characteristic of ............................ 268
A/D converter, note on using................................ 280
A/D converter, other note on using ...................... 280
A/D converter, successive approximation conversion
type ................................................................ 3
access mode .......................................................... 69
addition and subtraction instruction...................... 410
addressing area, direct........................................... 25
addressing mode code......................................... 405
architecture, 32-bit ................................................. 30
architecture, RISC.................................................. 30
area mode register 0 (AMD0), bit function of ....... 121
area mode register 0 (AMD0), configuration of .... 121
area mode register 1 (AMD1), bit function of ....... 123
area mode register 1 (AMD1), configuration of .... 123
area mode register 32 (AMD32), bit function of ... 124
area mode register 32 (AMD32), configuration of 124
area mode register 4 (AMD4), bit function of ....... 125
426
area mode register 4 (AMD4), configuration of.... 125
area mode register 5 (AMD5), bit function of ....... 126
area mode register 5 (AMD5), configuration of.... 126
area select register (ASR) and area mask register
(AMR), configuration of.............................. 118
arithmetic operation ............................................... 46
assembler source, example of ............................. 109
asynchronous (start-stop) mode, format of data
transferred in.............................................. 257
asynchronous mode (start-stop) .......................... 243
automatic algorithm, execution status of.............. 353
automatic erase operation status......................... 365
automatic wait cycle of CBR refresh .................... 192
automatic wait cycle timing chart ......................... 171
automatic wait cycle timing chart in usual DRAM
interface ..................................................... 181
automatic write operation status .......................... 365
automatic write/erase operation status ................ 366
available type ........................................................... 5
B
basic read cycle timing chart................................ 162
basic write cycle timing chart ............................... 164
baud rate and U-TIMER reload value, sample
setting for ................................................... 265
baud rate calculation............................................ 243
Bit......................................................................... 284
bit operation instruction........................................ 411
bit ordering ............................................................. 42
bit search module..................................................... 4
bit search module register.................................... 292
bit search module, block diagram of .................... 292
block diagram of MB91F109, general ...................... 6
block that uses peripheral clock............................. 89
branch .................................................................... 46
branch instruction with delay slot ........................... 48
branch instruction with delay slot, restriction on .... 50
branch instruction with delay slot, theory of
operation of.................................................. 48
branch instruction without delay slot ...................... 51
branch instruction without delay slot, theory of
operation of.................................................. 51
built-in adder .......................................................... 30
burst transfer mode.............................................. 337
bus access, usual ................................................ 159