Hyper Dram Interface: Read; Figure 4.17-32 Example Of Hyper Dram Interface Read Timing Chart - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 4 BUS INTERFACE

4.17.17 Hyper DRAM Interface: Read

This section provides a hyper DRAM interface timing chart.
Hyper DRAM Interface: Read Timing Chart
Bus width: 16 bits, access: words

Figure 4.17-32 Example of Hyper DRAM Interface Read Timing Chart

Q1
CLK
1) 1CAS/2WE
A24-00 X
D31-24
D23-16
RAS
CAS
WEL
WEH
RDX
(DACK0)
(EOP0)
[Explanation of operation]
• Column addresses are output in Q4HR cycles.
• CAS is asserted at the falling edge of Q4HR and negated at the rising edge of Q4HR.
• D31 to D16 are fetched at the falling edge of CAS to be output in the Q4HR cycle next to that
in which the corresponding column address is output.
• After a read cycle ends, at least one idle clock cycle is inserted so as to prevent conflicts
between the external data buses.
• DACK0 to DACK2 and E0P0 to E0P2 are output at the same time as CAS.
188
Q2 Q3 Q4HR
row.adr. col.0 col.2
Read0
Read1
Q4HR Q4HR Q4HR
col.4 col.6
Read2 Read4
Read3 Read5
High
High
High
speed
speed
speed
page
page
page
Idle
Q4HR Q1
X
Read6
Read7
Outside page
High
speed
page
Q3
row.a