Figure 3.15-1 Example Of Pll Clock Setting; Figure 3.15-2 Clock System Reference Diagram - Fujitsu MB91F109 FR30 Hardware Manual

• The peripheral operating frequency must not exceed 25 MHz.
• Design software so that 100 microseconds or more are allowed until oscillation stabilizes
after the PLL VC0 restarts. Do not allow cache on/off to cause a wait time shortage.
Clock System Reference Diagram
12.5MHz
Input of oscillation
Example of Assembler Source
; ************************************************************
; PLL Sample Program
; ************************************************************
; Load Setting Data
ldi:20 #GCR, R0
ldi:20 #PCTR,R1
ldi:8 #GCR_MASK,R2
ldi:8 #PCTR_MASK,R3
ldub @R0,R4
ldub @R1,R5
st PS,@-R15
stilm #0x0
;
and R4,R2
beq CHC_0
bra CHC_1
CHC_0:
borl #0001B,@r0

Figure 3.15-2 Clock System Reference Diagram

1/2
PLL
50MHz
1/2
VSTP
25MHz
STAND-BY
1/2
12.5MHz
; GCR_MASK = 0000 0001 b
; PCTR_MASK = 0000 1000 b
; read GCR register
; read PCTR register
; push processor status
; disable interrupt
; to 1/2 clock
Input of divide-by-two clock
1/2
Input of PLL clock
SLCT1,0
- -
0 1
0 0
PCTR register
@r0=GCR register
3.15 Example of PLL Clock Setting
CHC DBLON
1 DBLACK
0
GCR register
CPU
Peripheral
109