Dram Control Register 4/5 (Dmcr4/5); Table 4.10-1 Page Size Of Dram Connected - Fujitsu MB91F109 FR30 Hardware Manual

4.10 DRAM Control Register 4/5 (DMCR4/5)

DRAM control registers 4 and 5 (DMCR4 and DMCR5) control the DRAM interface for
areas 4 and 5 and are valid only when the DRME bits of AMD4 and AMD5 are set to "1".
Configuration of DRAM Control Register 4/5 (DMCR4/5)
DRAM control register 4/5 are configured as follows:
DMCR4
Address: 0000 062C
H
DMCR5
Address: 0000 062E
H
Bit Functions of DRAM Control Register 4/5 (DMCR4/5)
[bit 15 to 12] PGS 3 to 0 (PaGe size Select bit)
PGS3 to PGS0 specify the page size of the DRAM to be connected (see Table 4.10.1).

Table 4.10-1 Page Size of DRAM Connected

PGS3 to 0 Page size
0000 256
0001 512
0010 1024
0011 4096
0100 reserved
to
1111
The bus interface unit determines the row size (page size) by the values of PGS3 to PGS0
as well as the specified bus width. If an intrapage access occurs when the register allows a
page access mode, a high-speed page access is executed.
15 14 13
PGS3 PGS2 PGS1 PGS0 Q1W Q4W DSAS HYPR
7 6 5
PAGE C/W SLFR REFE PAR PERR PEIE
15 14 13
PGS3 PGS2 PGS1 PGS0 Q1W Q4W DSAS HYPR
7 6 5
PAGE C/W SLFR REFE PAR PERR PEIE
ROW Address
A31 to 16 A15 to 00
A31 to 16 A23 to 08
A31 to 16 A24 to 09
A31 to 16 A25 to 10
A31 to 16 A27 to 12
4.10 DRAM Control Register 4/5 (DMCR4/5)
12 11 10 9
4 3 2 1
12 11 10 9
4 3 2 1
Column
address
A31 to 00
A31 to 00
A31 to 00
A31 to 00
8
initial value
00000000
0
initial value
0000000-
8
initial value
00000000
0
initial value
0000000-
Determine whether access
is within page
8-bit bus 16-bit bus
A31 to 08 A31 to 09
A31 to 09 A31 to 10
A31 to 10 A31 to 11
A31 to 12 A31 to 13
access
R/W
access
R/W
access
R/W
access
R/W
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