Fujitsu MB91F109 FR30 Hardware Manual page 440

APPENDIX E Instructions
Delayed-Branch Instructions
Table E.1-12 Delayed Branch Instructions
Mnemonic Type
JMP:D @Ri
CALL:D label12
CALL:D @Ri
RET:D
BRA:D label9
BNO:D label9
BEQ:D label9
BNE:D label9
BC:D label9
BNC:D label9
BN:D label9
BP:D label9
BV:D label9
BNV:D label9
BLT:D label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D label9
BHI:D label9
(Notes)
• The assembler calculates and sets values in the rel11 and rel8 fields of the hardware
specification as follows:
(label12-PC-2)/2 -> rel11, (label9-PC-2)/2 -> rel8: Label12 and label9 are signed.
• The next instruction (delay slot) is executed before delayed branch is executed.
• All 1-cycle instructions including the a, b, c, and d cycle instructions can be placed in the
delay slot. Instructions of two or more cycles cannot be placed.
416
OP CYCLE
E 9F-0 1
F D8 1
E 9F-1 1
E 9F-2 1
D F0 1
D F1 1
D F2 1
D F3 1
D F4 1
D F5 1
D F6 1
D F7 1
D F8 1
D F9 1
D FA 1
D FB 1
D FC 1
D FD 1
D FE 1
D FF 1
NZVC
---- Ri --> PC
---- PC+4-->RP ,PC+2+(label12-PC-2) -->PC
---- PC+4-->RP ,Ri-->PC
---- RP --> PC
---- PC+2+(label9-PC-2) -->PC
---- Nonbranch
---- if(Z==1) then
PC+2+(label9-PC-2) -->PC
---- s/Z==0
---- s/C==1
---- s/C==0
---- s/N==1
---- s/N==0
---- s/V==1
---- s/V==0
---- s/V xor N==1
---- s/V xor N==0
---- s/(V xor N) or Z==1
---- s/(V xor N) or Z==0
---- s/C or Z==1
---- s/C or Z==0
Operation Remarks
Return