Interrupt Controller Block Diagram; Figure 8.2-1 Block Diagram Of The Interrupt Controller - Fujitsu MB91F109 FR30 Hardware Manual

Fr30 series 32-bit microcontroller
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8.2

Interrupt Controller Block Diagram

Figure 8.2-1 is an interrupt controller block diagram.
Interrupt Controller Block Diagram
NMI
RI00
RI47
(DLYIRQ)
*1: DLYI is the delayed interrupt module (See Chapter 7, "Delayed Interrupt Module," for more information.)
*2: INT0 is a wakeup signal for the clock controller in sleep or stop state.
*3: HLDCAN is a bus yield request signal to a bus master other than the CPU.

Figure 8.2-1 Block Diagram of the Interrupt Controller

INTO
*2
OR
NMI
processing
4
LEVEL check
ICR00
ICR47
*1
DLYI
Priority check
5
/
6
VECTOR check
/
R-BUS
8.2 Interrupt Controller Block Diagram
HLDREQ
cancel
request
LEVEL4 to 0
HLDCAN
*3
VCT5 to 0
227

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