Dram Relationships; Table 4.16-2 Functions And Bus Widths Of Dram Control Pins - Fujitsu MB91F109 FR30 Hardware Manual

4.16.4 DRAM Relationships

This section explains the DRAM relationships.
DRAM Control Pins
Table 4.16-2 lists the relationship between the pin functions and bus widths used in the DRAM
interface.

Table 4.16-2 Functions and Bus Widths of DRAM Control Pins

Pin name
RAS0
RAS1
CS0L
CS0H
CS1L
CS1H
DW0X
DW1X
4.16 Relationship between Data Bus Widths and Control Signals
Data bus in 16-bit mode
2CAS/1WE 1CAS/2WE
mode mode
Area 4 RAS Area 4 RAS
Area 5 RAS Area 5 RAS
Area 4 CASL Area 4 CAS
Area 4 Area 4 WEL
CASH
Area 5 CASL Area 5 CAS
Area 5 Area 5 WEL
CASH
Area 4 WE Area 4 WEH
Area 5 WE Area 5 WEH
Data bus in 8-bit
mode
Area 4 RAS •
Area 5 RAS
Area 4 CAS
Area 4 CAS
CASL: CAS corresponding
Area 5 CAS
Area 5 CAS
CASH: CAS
corresponding
Area 4 WE
Area 5 WE
WEL:
WEH: WE corresponding
Remarks
Correspondence
between "L" and "H"
and lower 1 bit (A0) of
address for data bus in
16-bit mode
• "L":"0"
• "H":"1"
to area containing
"0" in A0
to area containing
"1" in A0
WE corresponding
to area containing
"0" in A0
to area containing
"1" in A0
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