Fujitsu MB91F109 FR30 Hardware Manual page 221

stb
init_amd0 ldi:8
ldi:20
stb
init_amd1 ldi:8
ldi:20
stb
init_amd32 ldi:8
ldi:20
stb
init_amd4 ldi:8
ldi:20
stb
init_amd5 ldi:8
ldi:20
stb
init_dmcr4 ldi:20
ldi:20
sth
init_dmcr5 ldi:20
ldi:20
sth
init_rfcr ldi:20
4.19 Program Example for External Bus Operation
r0,@r1
#0x08,r0 //
#0x620,r1 //
r0,@r1 //
#0x0a,r0 //
#0x621,r1 //
r0,@r1 //
#0x49,r0 //
#0x622,r1 //
r0,@r1 //
#0x88,r0 //
#0x623,r1 //
r0,@r1 //
#0x88,r0 //
#0x624,r1 //
r0,@r1 //
#0x0c90,r0 //
//
#0x62c,r1 //
r0,@r1 //
#0x10c0,r0 //
//
#0x62e,r1 //
r0,@r1 //
#0x0205,r0 //
Write to dscr register
16-bit bus, 0-wait
amd0 register address setting
Write to amd0 register
16-bit bus, 2-wait
amd1 register address setting
Write to amd1 register
Usual, 16-bit bus, 1-wait
amd32 register address setting
Write to amd32 register
DRAM, 16-bit bus
amd4 register address setting
Write to amd4 register
DRAM, 16-bit bus
amd5 register address setting
Write to amd5 register
page size=256,Q1/Q4-wait,Page
1CAS-2WE, CBR, without parity
dmcr4 register address setting
Write to dmcr4 register
page size=512, without Q1/Q4-wait,
Page
2CAS-1WE, CBR, without parity
dmcr5 register address setting
Write to dmcr5 register
REL=2, without R1W/R3W-wait,
refresh, 1/8
197