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Automatic wait cycle: Any number of cycles (0 to 7) can be set for each area.
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Unused data and address terminals can be used as I/O ports.
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Support for little endian mode (selecting one of areas 1 to 5)
DRAM interface
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2-bank independent control (areas 4 and 5)
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Double CAS DRAM (normal DRAM interface), single CAS DRAM, and hyper DRAM
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Basic bus cycle: Five cycles in normal mode. Two-cycle access is enabled in high-speed
page mode.
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Programmable waveform: Automatic 1-cycle wait can be inserted into RAS or CAS.
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DRAM refresh
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CBR refresh (The interval can be set as desired using the 6-bit timer.)
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Self-refresh mode
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Support for 8-, 9-, 10-, or 12-line column address
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Choice between 2CAS/1WE and 2WE/1CAS
DMAC (DMA controller)
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Eight channels
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Transfer cause: External terminal or internal resource interrupt request
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Transfer sequence
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Step transfer or block transfer
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Burst transfer or continuous transfer
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Transfer data length: Selectable from 8, 16, and 32 bits
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A temporary stop is enabled by an NMI/interrupt request.
UART
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Independent three channels
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Full duplex double buffer
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Data length: 7 to 9 bits (no parity) or 6 to 8 bits (with parity)
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Choice between asynchronous (start-stop synchronization) communication and clock
asynchronous communication
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Multiprocessor mode
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Built-in 16-bit timer (U-Timer) as a baud rate generator, which can generate a desired baud
rates
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An external clock can be used as a transfer clock.
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Error detection: Parity error, frame error, and overrun
A/D converter (successive approximation conversion type)
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10-bit resolution, 4 channels
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Successive approximation conversion type: 5.6 s at 25 MHz
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Built-in sample and hold circuit
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Conversion mode:
Selectable from single conversion, scan conversion, and repeat
1.1 MB91F109 Characteristics
3
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