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CHAPTER 3 CLOCK GENERATOR AND CONTROLLER
3.6
Gear Control Register (GCR)
The gear control register (GCR) controls the gear functions of the CPU and peripheral
clocks.
Configuration of the Gear Control Register (GCR)
The configuration of the gear control register (GCR) is shown below:
00000484
Bit Functions of the Gear Control Register (GCR)
[bit 15,14] CCK1, 0
These bits specify the CPU gear cycle. The bits and the cycles selected by the bits have the
relationships shown in Table 3.6.1. These bits are initialized by resetting.
Table 3.6-1 CPU Machine Clock
CCK1
0
0
1
1
0
0
1
1
PLL: PLL oscillation frequency
Source oscillation: Input frequency from X0
[bit 13] DBLAK
This bit indicates the clock doubler operation mode. Since the bit is read only, a write
attempt is ignored. This bit is initialized by resetting.
Bus frequency switching involves a time lag.
operation has actually been changed.
function.
82
15
14
13
CCK1 CCK0 DBLAK DBLON PCK1
H
CCK0
CHC
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
12
11
10
09
PCK0
CPU machine clock
PLL
PLL
1/2
PLL
1/4
PLL
1/8
Source oscillation × 1 2
Source oscillation × 1/2
Source oscillation
1/2
Source oscillation × 1/2
This model does not support the clock doubler
08
Access
Initial value
110011-1
R/W
CHC
1/2
1/4
1/8 [Initial value]
This bit can be used to check whether
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