Figure 4.17-22 Example 2 Of Usual Dram Write Cycle Timing Chart; Figure 4.17-23 Example 3 Of Usual Dram Write Cycle Timing Chart - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 4 BUS INTERFACE
Bus width: 16 bits, access: bytes

Figure 4.17-22 Example 2 of Usual DRAM Write Cycle Timing Chart

CLK
1)1CAS/2WE
A24-00
D31-24
D23-16
RAS
CAS
WEL
WEH
2)2CAS/1WE
A24-00
D31-24
D23-16
RAS
CASL
CASH
WE
Bus width: 8 bits, access: half-words

Figure 4.17-23 Example 3 of Usual DRAM Write Cycle Timing Chart

Q1
CLK
A24-00 X
D31-24
D23-16
RAS
CAS
WE
180
Q1 Q2 Q3
X #0 row.adr.
#0
X
Upper address side
X #0 row.adr.
#0
X
Upper address side
Q2 Q3
#0 row.adr.
#0
Q4 Q5 Q1
#0 col.adr X
Lower address side
#0 col.adr X
Q4 Q5 Q1
#0 col.adr X #1 row.adr.
Q2 Q3 Q4
#1 row.adr. #1 col.adr
X
#1
#1 row.adr. #1 col.adr
#1
#1
Lower address side
Q2 Q3 Q4
#1 col.adr
X
Q5
Q5