Fujitsu MB91F109 FR30 Hardware Manual page 437

Immediate Value Setting or 16/32-Bit Immediate Value Transfer Instruction
Table E.1-7 Immediate Value Setting or 16/32-Bit Immediate Value Transfer Instruction
Mnemonic
LDI:32 #i32, Ri
LDI:20 #i20, Ri
LDI:8 #i8, Ri
*LDI #{i8|i20|i32},Ri*
*: When the immediate value is an absolute value, the assembler automatically selects i8, i20, or i32.
If the immediate value includes a relative value or external reference symbol, i32 is selected.
Memory Load Instructions
Table E.1-8 Memory Load Instructions
Mnemonic
LD @Rj, Ri
LD @(R13,Rj), Ri
LD @(R14,disp10), Ri
LD @(R15,udisp6), Ri
LD @R15+, Ri
LD @R15+, Rs
LD @R15+, PS
LDUH @Rj, Ri
LDUH @(R13,Rj), Ri
LDUH @(R14,disp9), Ri
LDUB @Rj, Ri
LDUB @(R13,Rj), Ri
LDUB @(R14,disp8), Ri
*: Special register Rs: TBR, RP, USP, SSP, MDH, MDL
(Notes)
The assembler calculates and sets values in the o8 and o4 fields of hardware specifications as
follows:
Disp10/4 --> o8, disp9/2 --> o8, disp8 --> o8: Disp10, disp9, and disp8 are signed.
Udisp6/4 --> o4: Udisp6 is unsigned.
Type OP Cycle
E 9F-8 3
C 9B 2
B C0 1
Type OP CYCLE
A 04 b
A 00 b
B 20 b
C 03 b
E 07-0 b
E 07-8 b
E 07-9 1+a+b
A 05 b
A 01 b
B 40 b
A 06 b
A 02 b
B 60 b
NZVC Operation
---- i32 --> Ri
---- i20 --> Ri
---- i8 --> Ri
{i8|i20|i32} --> Ri
NZVC Operation
---- (Rj) --> Ri
---- (R13 + Rj) --> Ri
---- (R14 + disp10) --> Ri
---- (R15 + udisp6) --> Ri
---- (R15) --> Ri,R15 + = 4
---- (R15) --> Rs,R15 + = 4
CCCC (R15) --> PS,R15 + = 4
---- (Rj) --> Ri
---- (R13 + Rj) --> Ri
---- (R14 + disp9) --> Ri
---- (Rj) --> Ri
---- (R13 + Rj) --> Ri
---- (R14 + disp8) --> Ri
APPENDIX E Instructions
Remarks
Upper 12 bits are zero-
expanded.
Upper 24 bits are zero-
expanded.
Remarks
Rs: special
register*
Zero expansion
Zero expansion
Zero expansion
Zero expansion
Zero expansion
Zero expansion
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