External Bus Request; Figure 4.17-38 Example Of Bus Control Release Timing Chart; Figure 4.17-39 Example Of Bus Control Acquisition Timing - Fujitsu MB91F109 FR30 Hardware Manual

4.17.21 External Bus Request

This section provides external bus request timing charts.
Bus Control Release
[Explanation of operation]
• When performing bus arbitration by BRQ and BGRNTX, set the BRE bit of EPCR0 to "1".
• When releasing bus control, set the corresponding pins to High-Z and assert BGRNTX one
cycle later.
Bus Control Acquisition
[Explanation of operation]
• When performing bus arbitration by BRQ and BGRNTX, set the BRE bit of EPCR0 to "1".
• When acquiring bus control, negate BGRNTX and activate each pin one clock later.

Figure 4.17-38 Example of Bus Control Release Timing Chart

CLK
A24-00
D31-16
RDX
BRQ
BGRNTX

Figure 4.17-39 Example of Bus Control Acquisition Timing

CLK
A24-00 high Z
D31-16 high Z
RDX high Z
BRQ
BGRNTX
#0:1 high Z
#0:1 high Z
high Z
1 cycle
1 cycle
4.17 Bus Timing
193