Table B-2 Interrupt Vectors (2/2) - Fujitsu MB91F109 FR30 Hardware Manual

Table B-2 Interrupt Vectors (2/2)

Interrupt cause
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Delay interrupt cause bit
System reservation (used by
3
REALOS) *
System reservation (used by
3
REALOS) *
Used for INT instruction
*1
*2
*3
Interrupt number
Decimal
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
to
255
The ICR is a register provided in the interrupt controller that sets an interrupt level for
each interrupt request. It is provided for each interrupt request.
The TBR is a register that indicates the first address of vector tables for EIT. The
address, given by adding an offset value specified for each TBR and EIT factor,
becomes a vector address.
When using the REALOS or FR, use the 0x40 and 0x41 interrupts for system codes.
Interrupt
Hexa-
level *1
decimal
2F ICR31
30 -
31 -
32 -
33 -
34 -
35 -
36 -
37 -
38 -
39 -
3A -
3B -
3C -
3D -
3E -
3F ICR47
40 –
41 –
42 –
to
FF
APPENDIX B Interrupt Vectors
TBR default
Offset
address *2
340 000FFF40
H
33C 000FFF3C
H
338 000FFF38
H
334 000FFF34
H
330 000FFF30
H
32C 000FFF2C
H
328 000FFF28
H
324 000FFF24
H
320 000FFF20
H
31C 000FFF1C
H
318 000FFF18
H
314 000FFF14
H
310 000FFF10
H
30C 000FFF0C
H
308 000FFF08
H
304 000FFF04
H
300 000FFF00
H
2FC 000FFEFC
H
2F8 000FFEF8
H
2F4 000FFEF4
H
to to
000 000FFC00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
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