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CHAPTER 10 UART
10.9 UART Interrupt Occurrence and Flag Setting Timing
The UART has five flags and two interrupt causes.
The five flags are PE, ORE, FRE, RDRF, and TDRE.
One of the two interrupt causes is for data reception and the other is for data
transmission.
Interrupt Occurrence and Flags
PE indicates a parity error, ORE indicates an overrun, and FRE indicates a framing error. Each
flag is set when the corresponding error occurs while data is received and is cleared when "0" is
written to REC of the SCR register.
RDRF is set when received data is loaded to the SIDR register and is cleared when the data is
read from the SIDR register. Mode 1 does not support the parity check function, and mode 2
does not support the parity check and framing error detection functions.
TDRE is set when the SODR register is emptied and ready to accept the next instance of write
data and is cleared when the next data item is written to the SODR register.
In data receptuion mode, PE, ORE, FRE, or RDRF is used to request an interrupt.
In data transmission, TDRE is used to request an interrupt.
Interrupt Flag Set Timing for Data Reception in Mode 0
When the last stop bit is detected after data reception/transfer is completed, the PE, ORE, FRE,
and RDRF flags are set to issue an interrupt request to the CPU. If PE, ORE, or FRE is active,
the SIDR data is invalid.
PE, ORE, FRE
Reception interrupt
260
Figure 10.9-1 ORE, FRE, and RDRF Set Timing (Mode 0)
Data
D6
RDRF
D7
Stop
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