4.17.19 Hyper DRAM Interface ................................................................................................................. 190
4.17.20 DRAM Refresh ............................................................................................................................. 191
4.17.21 External Bus Request ................................................................................................................... 193
I/O PORTS ................................................................................................. 201
5.1
Outline of I/O Ports ............................................................................................................................ 202
5.2
Port Data Register (PDR) .................................................................................................................. 203
5.3
5.4
6.1
6.2
6.3
6.4
6.5
External Interrupt Operation .............................................................................................................. 216
6.6
6.7
7.1
7.2
7.3
8.1
8.2
8.3
8.4
8.5
Priority Check .................................................................................................................................... 231
8.6
8.7
Hold Request Cancel Request .......................................................................................................... 235
8.8
U-TIMER .................................................................................................... 239
9.1
Overview of U-TIMER ........................................................................................................................ 240
9.2
U-TIMER Registers ............................................................................................................................ 241
9.3
U-TIMER Operation ........................................................................................................................... 243
CHAPTER 10 UART ......................................................................................................... 245
10.1 Overview of UART ............................................................................................................................. 246
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