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CHAPTER 10 UART
[bit 4] RDRF (Receive Data Register Full)
This bit is an interrupt request flag indicating that received data is stored in the SIDR
register.
The bit is set when received data is loaded to the SIDR register and cleared automatically
when the received data is read from the SIDR register.
0: No received data is stored. (Initial value)
1: Received data is stored.
[bit 3] TDRE (Transmitter Data Register Empty)
This bit is an interrupt request flag indicating that transmission data can be written to the
SODR register.
The bit is cleared when transmission data has been written to the SODR register. When the
written data is loaded to the transmission shifter and transmission begins, the bit is set again
to indicate that the next instance of transmission data can be written.
0: Transmission data cannot be written.
1: Transmission data can be written. (Initial value)
[bit 2] (reserved)
[bit 1] RIE (Receiver Interrupt Enable)
This bit controls receiver interrupts.
0: Disable interrupts. (Initial value)
1: Enable interrupts.
<Note>
The causes of receiver interrupts include indication of normal data reception by RDRF in
addition to the errors indicated by PE, ORE, and FRE.
[bit 0] TIE (Transmitter Interrupt Enable)
This bit controls transmitter interrupts.
0: Disable interrupts. (Initial value)
1: Enable interrupts.
<Note>
Transmitter interrupts are caused by indicating transmission requests by TDRE.
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