Fujitsu MB91F109 FR30 Hardware Manual page 18

Figure 4.17-12 Example 5 of Write Cycle Timing Chart .................................................................................. 169
Figure 4.17-13 Example of Read and Write Combination Cycle Timing Chart ............................................... 170
Figure 4.17-14 Example of Automatic Wait Cycle Timing Chart ..................................................................... 171
Figure 4.17-15 Example of External Wait Cycle Timing Chart ........................................................................ 172
Figure 4.17-16 Example of Usual DRAM Interface Read Timing Chart .......................................................... 173
Figure 4.17-17 Example of Usual DRAM Interface Write Timing Chart .......................................................... 175
Figure 4.17-18 Example 1 of Usual DRAM Read Cycle Timing Chart ............................................................ 177
Figure 4.17-19 Example 2 of Usual DRAM Read Cycle Timing Chart ............................................................ 178
Figure 4.17-20 Example 3 of Usual DRAM Read Cycle Timing Chart ............................................................ 178
Figure 4.17-21 Example 1 of Usual DRAM Write Cycle Timing Chart ............................................................ 179
Figure 4.17-22 Example 2 of Usual DRAM Write Cycle Timing Chart ............................................................ 180
Figure 4.17-23 Example 3 of Usual DRAM Write Cycle Timing Chart ............................................................ 180
Figure 4.17-24 Example of Automatic Wait Cycle Timing Chart in Usual DRAM Interface ............................ 181
Figure 4.17-25 Example 1 of DRAM Interface Timing Chart in High-Speed Page Mode ............................... 182
Figure 4.17-26 Example 2 of DRAM Interface Timing Chart in High-Speed Page Mode ............................... 182
Figure 4.17-27 Example 3 of DRAM Interface Timing Chart in High-Speed Page Mode ............................... 183
Figure 4.17-28 Example 4 of DRAM Interface Timing Chart in High-Speed Page Mode ............................... 184
Figure 4.17-29 Example of Single DRAM Interface Read Timing Chart ......................................................... 185
Figure 4.17-30 Example of Single DRAM Interface Write Timing Chart ......................................................... 186
Figure 4.17-31 Example of Single DRAM Interface Timing Chart ................................................................... 187
Figure 4.17-32 Example of Hyper DRAM Interface Read Timing Chart ......................................................... 188
Figure 4.17-33 Example of Hyper DRAM Interface Write Timing Chart .......................................................... 189
Figure 4.17-34 Example of Hyper DRAM Interface Timing Chart ................................................................... 190
Figure 4.17-35 Example of CAS before RAS (CBR) Refresh Timing Chart .................................................... 191
Figure 4.17-36 Example of Timing Chart of CBR Refresh Automatic Wait Cycle ........................................... 192
Figure 4.17-37 Example of Selfrefresh Timing Chart ...................................................................................... 192
Figure 4.17-38 Example of Bus Control Release Timing Chart ...................................................................... 193
Figure 4.17-39 Example of Bus Control Acquisition Timing ............................................................................ 193
Figure 4.18-1 Example of Timing Chart for 2X Clock (BW-16bit, Access-Word Read) ................................ 194
Figure 4.18-2 Example of Timing for 1X Clock (BW-16bit, Access-Word Read) .......................................... 195
Figure 5.1-1 Basic I/O Port Block Diagram ................................................................................................. 202
Figure 6.1-1 External Interrupt/NMI Controller Registers ............................................................................ 212
Figure 6.1-2 External Interrupt/NMI Controller Block Diagram .................................................................... 212
Figure 6.5-1 External Interrupt Operation ................................................................................................... 216
Figure 6.6-1 Clearing the Interrupt Cause Hold Circuit at Level Setting for the Interrupt Request Mode ... 217
Figure 6.6-2 Input of an Interrupt Cause in Interrupt Enable Mode and a Request Issued to the Interrupt
Controller ................................................................................................................................ 217
Figure 6.7-1 NMI Request Detection Block ................................................................................................. 218
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