Fujitsu MB91F109 FR30 Hardware Manual page 21

TABLES
Table 1.4-1 FBGA Package Pin Names ....................................................................................................... 13
Table 1.5-1 Pin Functions (1/5) .................................................................................................................... 14
Table 1.5-2 Pin Functions (2/5) .................................................................................................................... 15
Table 1.5-3 Pin Functions (3/5) .................................................................................................................... 17
Table 1.5-4 Pin Functions (4/5) .................................................................................................................... 18
Table 1.5-5 Pin Functions (5/5) .................................................................................................................... 20
Table 1.6-1 I/O circuit format (1/2) ................................................................................................................ 22
Table 1.6-2 I/O circuit format (1/2) ................................................................................................................ 23
Table 2.8-1 Interrupt Level .......................................................................................................................... 54
Table 2.8-2 Assignments of Interrupt Causes and Interrupt Vectors ............................................................ 56
Table 2.8-3 Vector Table ............................................................................................................................. 61
Table 2.8-4 Priority for EIT Event Acceptance and Masking Other Events .................................................. 62
Table 2.8-5 EIT Handler Execution Order .................................................................................................... 63
Table 2.10-1 Mode Pins and Setting Modes ................................................................................................... 69
Table 2.10-2 Bus Mode Setting Bit and the Function .................................................................................... 70
Table 3.2-1 Watchdog Timer Cycles Specified by WT1 and WT0 ................................................................ 77
Table 3.3-1 Oscillation Stabilization Wait Time Specified by OSC1 and OSC0 ........................................... 79
Table 3.6-1 CPU Machine Clock .................................................................................................................. 82
Table 3.6-2 Peripheral Machine Clock .......................................................................................................... 83
Table 3.7-1 Watchdog Timer Cycles Specified by WT1 and WT0 ................................................................ 85
Table 3.10-1 Types of Operation in Standby Mode ........................................................................................ 90
Table 3.14-1 Operating Frequency Combinations Depending on whether the Clock Doubler
Function is Enabled or Disabled .............................................................................................. 107
Table 4.3-1 Correspondence between Chip Select Areas and Selectable Bus Interfaces ......................... 116
Table 4.10-1 Page Size of DRAM Connected .............................................................................................. 127
Table 4.10-2 Combinations of Bus Widths Available in Areas 4 and 5 ......................................................... 129
Table 4.15-1 Mode Setting Using the Combination of Bits (LE2, LE1, and LE0) ........................................ 138
Table 4.16-1 Relationship between Data Bus Widths and Control Signals .................................................. 140
Table 4.16-2 Functions and Bus Widths of DRAM Control Pins ................................................................... 155
Table 4.16-3 Page Size Select Bits .............................................................................................................. 156
Table 5.4-1 External Bus Functions to be Selected (1/4) ........................................................................... 205
Table 5.4-2 External Bus Functions to be Selected (2/4) ........................................................................... 206
Table 5.4-3 External Bus Functions to be Selected (3/4) ........................................................................... 207
Table 5.4-4 External Bus Functions to be Selected (4/4) ........................................................................... 209
Table 6.4-1 External Interrupt Request Mode ............................................................................................. 215
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