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CHAPTER 16 FLASH MEMORY
Program (Write)
In CPU programming mode, data is basically written in half-word units. The write operation is
performed in four cycles of bus operation. The command sequence has two "unlock" cycles,
which are followed by a Write Setup command and a write data cycle. Writing to memory starts
in the last write cycle.
After an automatic write algorithm command sequence was executed, it becomes unnecessary
to control the flash memory externally. The flash memory itself internally generates write pulses
to check the margin of the cells to which data is written. The data polling function compares bit
7 of the original data with bit 7 of the written data, and if these bits are the same, the automatic
write operation ends (see "Hardware sequence flag," in Section 16.7, "Execution Status of the
Automatic Algorithm").
accepts no more write addresses. After that, the flash memory requests the next valid address.
In this manner, the data polling function indicates a write operation in memory.
During a write operation, all commands written to the flash memory are ignored. If a hardware
reset starts during write operation, the data at the address for writing may become invalid.
Writing operations can be performed in any address sequence and outside of sector
boundaries. However, write operations cannot change a data item "0" to "1". If a "0" is
overwritten with a "1", the data polling algorithm either determines that the elements are
defective, or that "1" has been written. In the latter case, however, the respective data item is
read as "0" in reset or read mode. A data item "0" can be changed to "1" only after an erase
operation.
Erase Chip
The Erase Chip command sequence ("erase all sectors simultaneously") is executed in six
access cycles. First, two "unlock" cycles are executed, then a "Setup" command is written.
After two more "unlock" cycles, the Erase Chip command is entered.
During the Erase Chip command sequence, the user does not have to write to flash memory
before the erase operation. When the automatic erase algorithm is executed, flash memory
checks cell states by writing a pattern of zeros before automatically erasing the contents of all
cells (preprogram). In this operation, flash memory does not have to be controlled externally.
The automatic erase operation starts with the write operation of the command sequence and
ends when bit 7 is set to "1", where flash memory returns to the read mode. The chip erase
time can be expressed as follows: time for sector erase x number of all sectors + time for writing
to the chip (preprogram).
Sector Erase
The Sector Erase command sequence is executed in six access cycles. First, two "unlock"
cycles are executed, then a "Setup" command is written. After two more "unlock" cycles, the
Sector Erase command is entered in the sixth cycle for starting the sector erase operation. The
next Sector Erase command can be accepted within a time-out period of 50 s after the last
Sector Erase command is written.
As already mentioned, multiple Sector Erase commands can be accepted during the six bus
cycles of the writing operation. During the command sequence, Sector Erase commands (30H)
for sectors whose contents are to be erased simultaneously are written consecutively to the
addresses for these sectors. The sector erase operation itself starts from the end of the time-
out period of 50
multiple sectors are erased simultaneously, the subsequent Sector Erase commands must be
input within the 50 s time-out period to ensure that they are accepted. For checking whether
the succeeding Sector Erase command is valid, read bit 3 (see "Hardware sequence flag," in
Section 16.7, "Execution Status of the Automatic Algorithm").
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The automatic write operation then returns to the read mode and
s after the last Sector Erase command is written. When the contents of
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