Table of Contents
Advertisement
CHAPTER 15 DMAC
Required pin input mode: edge, descriptor address: external
CLK
DREQn
Addr pin
Data pin
RDXD
WRnX
DACK
EOP
Required pin input mode: edge, descriptor address: internal
CLK
DREQn
Addr pin
Data pin
RDXD
WRnX
DACK
EOP
<Note>
The section from when a DREQn is generated to when the DMAC operation starts shows the
case where the DMAC operation starts first.
The DMAC operation may be delayed because the CPU fetches instructions and accesses
data, thereby creating bus contention.
344
#0H
#0L
#1H
#0H
#0L
(A)
S
S
#1L
#2H
#1H
#1L
#2H
(A)
#2L
S
#2L
S
Advertisement
Table of Contents
