CHAPTER 2 CPU
2.4
Data Structure
FR-series data is mapped as follows:
• Bit ordering: Little endian
• Byte ordering: Big endian
Bit Ordering
The FR series uses little endian for bit ordering.
Figure 2.4.1 shows data mapping in bit ordering mode.
bit
31
30
MSB
Byte Ordering
The FR series uses big endian for byte ordering.
Figure 2.4.2 shows data mapping in byte ordering mode.
Address n
Address (n+1)
Address (n+2)
Address (n+3)
42
Figure 2.4-1 Data Mapping in Bit Ordering Mode
29
27
25
23
21
28
26
24
22
20
Figure 2.4-2 Data Mapping in Byte Ordering Mode
Memory
bit
7
0
10101010
11001100
11111111
00010001
19
17
15
13
11
18
16
14
12
10
MSB
bit31
23
10101010
11001100
9
7
5
3
1
8
6
4
2
0
LSB
15
7
11111111
00010001
LSB
0