Table of Contents
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CHAPTER 3
This chapter provides detailed information on the generation and control of clock
pulses that control the MB91F109.
3.1 Outline of Clock Generator and Controller
3.2 Reset Reason Resister (RSRR) and Watchdog Cycle Control Register
3.3 Standby Control Register (STCR)
3.4 DMA Request Suppression Register (PDRR)
3.5 Timebase Timer Clear Register (CTBR)
3.6 Gear Control Register (GCR)
3.7 Watchdog Timer Reset Delay Register (WPR)
3.8 PLL Control Register (PCTR)
3.9 Gear Function
3.10 Standby Mode (Low Power Consumption Mechanism)
3.11 Watchdog function
3.12 Reset source hold circuit
3.13 DMA suppression
3.14 Clock doubler function
3.15 Example of PLL Clock Setting
CLOCK GENERATOR AND CONTROLLER
(WTCR)
73
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