Single Dram Interface; Figure 4.17-31 Example Of Single Dram Interface Timing Chart - Fujitsu MB91F109 FR30 Hardware Manual

4.17.16 Single DRAM Interface

This section provides a single DRAM interface timing chart.
Single DRAM Interface Timing Chart
Combination of single DRAM and basic bus cycle, CS switch-over

Figure 4.17-31 Example of Single DRAM Interface Timing Chart

Q4SR
CLK
A24-00 col.
D31-24 Read
D23-16
Read
CS2X
CS4X
CS5X
RDX
WR0X
CS4:RAS
CS4:CASL
CS4:CASH
CS4:WE
CS5:RAS
CS5:CASL
CS5:CASH
CS5:WE
CS5 Single
[Explanation of operation]
• When a bus cycle starts from a high-speed page, RDX in a read cycle goes down to "L" from
the rising edge of Q4SR and is negated when the Q4SR cycle ends. In a write cycle, it goes
down to "L" from the rising edge of WE (including WEL and WEH) Q4SW and is negated
when the Q4SW cycle ends.
• CS4X and CS5X change at the same time as the output address. When a bus cycle starts
from a high-speed page, they change from the Q4SR and Q4SW cycles as with the column
address.
BA1 BA2
Idle
CS2X basic bus
Write
Write
CS2 usual
Q1 Q2 Q3
X row.adr.
Write
Write
CS4 Single
4.17 Bus Timing
Idle
Q4SW Q4SR
col. col.
Read
Read
Q4SR
col.
Read
Read
CS5
187