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2.3.3
Program Status Register (PS)
The program status register holds the program status in three parts, ILM, SCR, and
CCR. The undefined bits are all reserved. When the register is read, 0 is always read
from these bits.
No data can be written to this register.
Program Status Register (PS)
The configuration of the program status register (PS) is shown below:
31
Condition code register (CCR)
The configuration of the condition code register (CCR) is shown below:
[bit 5] S: Stack flag
This bit specifies the stack pointer used as R15.
0: Uses SSP as R15.
1: Uses USP as R15.
Set the bit to 0 when the RETI instruction is executed.
[bit 4] I: Interrupt enable flag
This bit enables or disables a user interrupt request.
0: Disables user interrupts.
1: Enables user interrupts.
This bit is cleared to 0 by resetting.
20
4
7
6
5
S
I
The bit is automatically set to 0 when EIT occurs.
This bit is cleared to 0 by resetting.
The bit is cleared to 0 when the INT instruction is executed.
(The value before the bit is cleared is saved to the stack.)
The masking of user interrupt requests is controlled by the value held in the ILM.
16
10 8 7
ILM
SCR
3
1
0
2
V
C
N
Z
2.3 Programming Model
0
CCR
[Initial value]
--00XXXX
B
39
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