Timing Charts Of The Descriptor Access Block - Fujitsu MB91F109 FR30 Hardware Manual

15.9.1 Timing Charts of the Descriptor Access Block

This section shows timing charts of the descriptor access block.
Descriptor Access Block
Required pin input mode: level, descriptor address: external
CLK
DREQn
Addr pin
Data pin
RDXD
WRnX
DACK
EOP
Required pin input mode: level, descriptor address: internal
Interanl KB
CLK
DREQn
Addr pin
Data pin
RDXD
WRnX
DACK
EOP
#0H #0L #1H
#0H #0L
(A)
S
S
15.9 DMAC Timing Charts
#1L #2H
#1H #1L #2H
(A)
#2L S
#2L S
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