Bus width: 8 bits, access: half-words
Figure 4.17-6 Example 4 of Read Cycle Timing Chart
BA1
CLK
A24-00
#0
D31-24
#0
D23-16
RDX
Bus width: 8 bits, access: bytes
Figure 4.17-7 Example 5 of Read Cycle Timing Chart
BA1
BA2
CLK
A24-00
#0
D31-24
#0
D23-16
RDX
BA2
BA1
BA2
#1
#1
BA1
BA2
#1
#1
BA1
BA2
BA1
#2
#3
#2
BA1
BA2
BA1
#2
#2
4.17 Bus Timing
BA2
#3
BA
#3
#3
167