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CHAPTER 4 BUS INTERFACE
[bit 11] Q1W (Q1 wait bit)
The Q1W bit specifies whether to extend the Q1cycle (the "H" interval of RAS), specified at
DRAM access time, by one cycle.
0: Does not extend Q1 cycle (initial value).
1: Extends Q1 cycle.
[bit 10] Q4W (Q4 wait bit)
The Q4W bit specifies whether to extend the Q4 cycle (the "L" interval of CAS), specified at
DRAM access time, by one cycle. This bit is valid only when the DSAS bit (bit 9) is 0.
0: Does not extend Q4 cycle (initial value).
1: Extends Q4 cycle.
[bit 9] DSAS (Double/Single cas Access cycle Select bit)
The DSAS bit selects one cycle (single CAS access) or two cycles (double CAS access) for
CAS access when a high-speed DRAM access mode is used.
0: Double CAS access (initial value)
1: Single CAS access
[bit 8] HYPR (HYPeR page mode enable)
The HYPR bit is set to connect a DRAM with a hyper page mode to the outside.
0: Double/single CAS DRAM (initial value)
1: DRAM with hyper page mode
[bit 7] PAGE (PAGe Enable bit)
The PAGE bit specifies whether to enable the high-speed page mode.
0: Disables high-speed page mode (random access operation by initial value).
1: Enables high-speed page mode (enables high-speed access to intrapage specified by
PGS3 to PGS0).
[bit 6] C/W (1CAS-2WE/2CAS-1WE Select bit)
The C/W bit selects the 1CAS-2WE or 2CAS-1WE type memory interface when a 16-bit or
greater bus width is used.
0: 1CAS-2WE interface (initial value)
1: 2CAS-1WE interface
[bit 5] SLFR (SeLF Refresh bit)
When the SLFR bit is set to "1", the DRAM enters the selfrefresh mode. The selfrefresh
mode is enabled when the SLFR bit of DMCR4 or DMCR5 is set to "1", regardless of areas 4
and 5.
0: Disables selfrefresh mode (initial value).
1: Enables selfrefresh mode.
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