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CHAPTER 2 CPU
2.8.8
EIT Operation
This section explains EIT operation.
Suppose the transfer source "PC" appearing in the following explanation indicates the
address of the instruction that detected an EIT event.
"Next instruction address" appearing in the following explanation means the address
of the instruction that detected EIT as follows:
• LDI: 32 --- PC + 6
• LDI: 20, COPOP, COPLD, COPST, COPSV --- PC + 4
• Other instructions --- PC + 2
Operation for User Interrupt/NMI
When a user interrupt or user NMI interrupt request is issued, the system checks whether to
accept the request as follows:
Checking whether to accept an interrupt request
1. The interrupt levels of the requests issued concurrently are compared, and the request
having the highest level (smallest numeric value) is selected. For maskable interrupts, the
values held by the corresponding ICRs are used for the compared levels. For nonmaskable
interrupts, the constants defined in advance are used.
2. When multiple interrupt requests have the same level, the interrupt request having the
smallest interrupt number is selected.
3. The interrupt level of the selected interrupt request is compared with the level mask value
indicated by the ILM.
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•
4. If the I flag is 0 when the selected interrupt request is a maskable interrupt, the interrupt
request is masked and not accepted. If the I flag is 1, proceed to step 5).
•
5. If the above conditions are satisfied, the interrupt request is accepted at the end of
processing of the current instruction.
If a user interrupt/NMI request is accepted when an EIT request is detected, the CPU, using the
interrupt number corresponding to the accepted interrupt request, operates as follows:
The parentheses ( ) in [Operation] represent the address indicated by the register.
64
When the interrupt level equals or exceeds the level mask value, the interrupt request is
masked and not accepted.
When the interrupt level is less than the level mask value, proceed to step 4).
When the selected interrupt request is an NMI, proceed to step 5) regardless of the I flag
value.
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