Fujitsu MB91F109 FR30 Hardware Manual page 91

Coprocessor Nonexistent Trap
If a coprocessor instruction that attempts to use a coprocessor that is not installed is executed,
a coprocessor nonexistent trap occurs.
[Operation]
SSP - 4 --> SSP
PS --> (SSP)
SSP - 4 --> SSP
Next instruction address --> (SSP)
"0" --> S flag
(TBR + 3E0
Coprocessor Error Trap
If an error occurs while a coprocessor is used, a coprocessor error trap occurs when a
coprocessor instruction that uses the coprocessor is executed afterwards. (No coprocessor is
installed in this product.)
[Operation]
SSP - 4 --> SSP
PS --> (SSP)
SSP - 4 --> SSP
Next instruction address --> (SSP)
"0" --> S flag
(TBR + 3DC
Operation for RETI Instruction
The RETI instruction is used to return from the EIT processing routine.
[Operation]
(R15) --> PC
R15 + 4 --> R15
(R15) --> PS
R15 + 4 --> R15
The RETI instruction must be executed while the S flag is 0.
) --> PC
H
) --> PC
H
2.8 EIT (Exception, Interrupt, and Trap)
67