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CHAPTER 2 CPU
Operation for Step-trace-trap
After the T flag in the PS SCR is set to enable the step-trace function, a trap occurs every time
an instruction is executed, resulting in a break.
A step-trace-trap is detected under the following conditions:
•
T flag = 1
•
Instruction other than a delayed branch instruction
•
During execution of something other than the INTE instruction or step-trace-trap processing
routine
If the above conditions are met, a break occurs at the end of the current instruction operation.
[Operation]
SSP - 4 --> SSP
PS --> (SSP)
SSP - 4 --> SSP
Next instruction address --> (SSP)
"00100" --> ILM
"0" --> S flag
(TBR + 3CC
After the T flag in the PS SCR is set to enable the step-trace function, user NMIs and user
interrupts are inhibited. No INTE EIT occurs, either.
Operation for Undefined-instruction Exception
If an instruction is found undefined during instruction decoding, an undefined-instruction
exception occurs.
An undefined-instruction exception occurs under the following conditions:
•
The instruction is found undefined during instruction decoding.
•
The instruction is provided at a location other than a delay slot (not immediately after a
delayed branch instruction).
If the above conditions are met, an undefined-instruction exception occurs and results in a
break.
[Operation]
SSP - 4 --> SSP
PS --> (SSP)
SSP - 4 --> SSP
PC --> (SSP)
"0" --> S flag
(TBR + 3C4
The address of the instruction that detected the undefined-instruction exception is saved to the
PC.
66
) --> PC
H
) --> PC
H
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