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15.9.3 Transfer Stop Timing Charts in Continuous Transfer Mode
This section shows transfer stop timing charts in continuous transfer mode.
Transfer Stop in Continuous Transfer Mode (When Either Address is Unchanged) for 16-Bit or 8-Bit
Data
Transfer source area: external, transfer destination area: external
CLK
DREQn
Addr pin
Data pin
RDXD
WRnX
DACK
EOP
Transfer source area: external, transfer destination area: internal RAM
CLK
DREQn
Addr pin
Data pin
RDXD
WRnX
DACK
EOP
Transfer source area: internal RAM, transfer destination area: external
CLK
DREQn
Addr pin
Data pin
RDXD
WRnX
DACK
EOP
D
S
D
S
W
S
S
D
D
D
D
D
D
W
W
W
D
#0H
#1/2H
D
#0H
#1/2H
W
W
S
#0H
S
#0H
W
#0H
#1/2H
#1/2L
#0H
#1/2H
#1/2L
W
W
W
15.9 DMAC Timing Charts
#1/2L
#1/2L
W
W
#1/2L
#1/2H
#1/2H
#1/2L
W
W
347
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