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UART Block Diagram
Figure 10.1-2 is a UART block diagram.
Control signal
From U-TIMER
External clock
SC
SI
(received data)
Reception status
check circuit
SMR
register
Figure 10.1-2 UART Block Diagram
Clock
selection
circuit
Reception clock
Reception
control circuit
Start bit
detection circuit
Reception
bit counter
Reception
parity counter
Reception shifter
Reception error generation
signal for DMA (to DMAC)
MD1
MD0
register
CS0
SCKE
SOE
Transmission clock
End of reception
SIDR
R - BUS
PEN
P
SBL
SCR
CL
A/D
REC
RXE
TXE
10.1 Overview of UART
Reception interrupt
(to CPU)
SC (clock)
Transmision interrupt
(to CPU)
Transmission
control circuit
Tranmission
start circuit
Tranmission
bit counter
Tranmission
parity counter
SO
(Transmit data)
Transmission shifter
Start of transmission
SODR
PE
ORE
FRE
SSR
RDRF
register
TDRE
RIE
TIE
Control signal
247
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