Hyper Dram Interface; Figure 4.17-34 Example Of Hyper Dram Interface Timing Chart - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 4 BUS INTERFACE

4.17.19 Hyper DRAM Interface

This section provides a hyper DRAM interface timing chart.
Hyper DRAM Interface Timing Chart
Combination of hyper DRAM and basic bus cycle, CS switch-over

Figure 4.17-34 Example of Hyper DRAM Interface Timing Chart

BA1
CLK
A24-00 CS2X basic bus
D31-24 Write
D23-16
Write
CS2X
CS4X
CS5X
RDX
WR0X
CS4:RAS
CS4:CASL
CS4:CASH
CS4:WE
CS5:RAS
CS5:CASL
CS5:CASH
CS5:WE
CS2 nomal
[Explanation of operation]
• When a bus cycle starts from a high-speed page, RDX in a read cycle goes down to "L" from
the falling edge of Q4HR and is negated when the Q4HR cycle ends. In a write cycle, it
goes down to "L" from the rising edge of WE (including WEL and WEH) Q4HW and is
negated when the Q4HW cycle ends.
• CS4X and CS5X change at the same time as the output address. When a bus cycle starts
from a high-speed page, they change from the Q4HR and Q4HW cycles as with the column
address.
190
BA2 Q1 Q2
X row.adr.
CS4 Hyper DRAM read
Q3 Q4HR Q4HR
col.adr.
Read
Read
Idle Q4HW Q4HR
col. col.
Write
Write
CS5 Hyper DRAM
write/read
Q4HR
col.
Read
Read