Fujitsu MB91F109 FR30 Hardware Manual page 441

Other Instructions
Table E.1-13 Other Instructions
Mnemonic Type
NOP
ANDCCR#u8
ORCCR #u8
STILM #u8
ADDSP #s10*1
EXTSB Ri
EXTUB Ri
EXTSH Ri
EXTUH Ri
LDM0 (reglist)
LDM1 (reglist)
*LDM (reglist)*2
STM0 (reglist)
STM1 (reglist)
*STM (reglist)*3
ENTER #u10*4
LEAVE
XCHB @Rj, Ri
*1: The assembler converts s10 to s8 by calculating s10/4, then sets the value in s8. S10 is signed.
*2: If a register from R0 to R7 is specified in reglist, LDM0 is created. If a register from R8 to R15 is
specified in reglist, LDM1 is created. Both LDM0 and LDM1 may be created.
*3: If a register from R0 to R7 is specified in reglist, STM0 is created. If a register from R8 to R15 is
specified in reglist, STM1 is created. Both STM0 and STM1 may be created.
*4: The assembler converts u10 to u8 by calculating u10/4, then sets a value in u8. U10 is signed.
OP CYCLE
E 9F-A 1
D 83 c
D 93 c
D 87 1
D A3 1
E 97-8 1
E 97-9 1
E 97-A 1
E 97-B 1
D 8C
D 8D
D 8E
D 8F
D 0F 1+a
E 9F-9 b
A 8A 2a
NZVC Operation
---- Remains unchanged.
CCCC CCR and u8 --> CCR
CCCC CCR or u8 --> CCR
---- i8 --> ILM
---- R15 += s10
---- Code expansion 8 --> 32
---- bits
---- Zero expansion 8 --> 32
---- bits
Code expansion 16 --> 32
bits
Zero expansion 16 --> 32
bits
---- (R15) -->reglist,
R15 increment
---- (R15) -->reglist,
R15 increment
---- (R15) -->reglist,
R15 increment
---- R15 decrement,
reglist-->(R15)
---- R15 decrement,
Reglist-->(R15)
---- R15 decrement,
reglist-->(R15)
---- R14 --> (R15 - 4),
R15 - 4 --> R14,
R15 - u10 --> R15
---- R14 + 4 --> R15,
(R15 - 4) --> R14
---- Ri --> TEMP
(Rj) --> Ri
TEMP --> (Rj)
APPENDIX E Instructions
Remarks
ILM immediate value setting
ADD SP instruction
Multiple load R0-R7
Multiple load R8-R15
Multiple load R0-R15
Multiple store R0-R7
Multiple store R8-R15
Multiple store R0-R15
Entrance processing of function
Exit processing of function
For semaphore management
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