Fujitsu MB91F109 FR30 Hardware Manual page 412

APPENDIX C Pin Status for Each CPU Status
Table C-3 Pin Status for 16-bit External Bus Length and 2CA1WR Mode (Continued)
Pin name Function
PA6 CLK
PB0 RAS0
PB1 CS0L
PB2 CS0H
PB3 DW0X
PB4 RAS1
EOP2
PB5 CS1L
DREQ2
PB6 CS1H
DACK2
PB7 DW1X
AN0 to AN0-3
AN3
PE0 to INT0-INT2
PE2
PE3 INT3
SC2
PE4 to DREQ0-
PE5 DREQ1
PE6 to DACK0-
PE7 DACK1
PF0 SI0, TRG0
PF1 SO0,
TRG1
PF2 SC0,
OCPA3
PF3 SI1, TRG2
388
During sleep
HIZX=0
P: Previous P, F: Previous
status retained status retained
F: CLK output
P: Previous P: Previous
status retained status retained
F: Previous F: Previous
value retained value retained
Executed when During refresh
DRAM pin is (*1)
set.
Previous status
retained
Input
possible
Previous status
retained
During stop
HIZX=1
Output Hi-Z/
Input fixed to 0
Input
possible
Bus release Reset time
(BGRNT)
CLK Output CLK
Output
P: Previous Output Hi-Z/
status retained Input
F: Previous value allowed for
retained all pins
Operation during
DRAM terminal
setting
Previous
value retained
Previous
value retained
Previous
value retained
Previous status
retained