Figure 10.9-4 Tdre Set Timing (Mode 0 Or 1); Figure 10.9-5 Tdre Set Timing (Mode 2) - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 10 UART
Interrupt Flag Set Timing for Data Transmission in Mode 0, 1, or 2
TDRE is cleared when data is written to the SODR register. After the written data is transferred
to the internal shift register and the SODR register is ready to accept the next item of write data,
TDRE is set again to issue an interrupt request to the CPU.
When "0" is written to TXE (or RXE in mode 2) of the SCR register during transmission, TDRE
of the SSR register is set to "1", thereby stopping the transmission shifter and inhibiting UART
transmit operation. When a "0" is written to TXE (or RXE in mode 2) of the SCR register during
transmission, data written to the SODR register before transmission is stopped is transmitted.
Writing to SODR
TDRE
SO interrupt
SO output
ST: Starter bit
Writing to SODR
TDRE
SO interrupt
SO output
262

Figure 10.9-4 TDRE Set Timing (Mode 0 or 1)

An interrupt request is issued to the CPU.
ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3
D0 to D7: Data bit

Figure 10.9-5 TDRE Set Timing (Mode 2)

An interrupt request is issued to the CPU.
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D0 to D7: Data bit
A/D
SP: Stop bit A/D: Address/data multiplexer