Fujitsu MB91F109 FR30 Hardware Manual page 455

power-on, input of source oscillation at.................. 27
power-on, pin condition at...................................... 27
PPDR register ...................................................... 340
priority check........................................................ 231
program (read) ..................................................... 362
program access ..................................................... 43
program counter (PC) ............................................ 36
program status (PS)............................................... 37
program status register (PS).................................. 39
PWM cycle setting register (PCSR) ..................... 308
PWM duty cycle setting register (PDUT) ............. 309
PWM operation .................................................... 315
PWM timer register .............................................. 301
PWM timer register (PTMR)................................. 310
PWM timer, characteristic of ................................ 300
PWM timer, general block diagram of.................. 302
PWM timer, L or H output from ............................ 320
Q
QFP-100, outside dimension ................................... 7
QFP-100, pin arrangement .................................... 10
R
read and write combination cycle timing chart ..... 170
read cycle timing chart ......................................... 166
read timing chart, hyper DRAM interface............. 188
read timing chart. single DRAM interface ............ 185
read/reset command ............................................ 361
ready/busy signal (RDY/BUSYX)......................... 364
receive operation ................................................. 257
recovery from sleep or stopped state..................... 28
refresh control register (RFCF), bit function of..... 130
refresh control register (RFCR), configuration of . 130
register of clock generator and controller............... 74
register, general-purpose................................. 33, 35
register, special................................................ 33, 36
releasing from external reset pin or software reset 68
reload register (UTIMR) ....................................... 241
reload timer .............................................................. 4
reset reason register (RSRR) and watchdog cycle
control register (WTCR), bit function of ....... 76
reset reason register (RSRR) and watchdog cycle
control register (WTCR), configuration of .... 76
reset request, return by way of .............................. 96
reset sequence ...................................................... 68
reset source hold circuit, block diagram of........... 101
reset source holding, setting for........................... 101
reset type ................................................................. 4
resetting, cause of.................................................. 68
resetting, initialization by ........................................68
resource instruction ..............................................422
resource interrupt request as a DMA transfer request,
using...........................................................339
RETI instruction, operation for................................67
return point (RP) .....................................................37
RISC architecture ...................................................30
ROM writer, writing by ..........................................353
row and column address ......................................156
RSTX pin, return by way of.....................................93
S
save/restore processing .......................................297
second word of descriptor ....................................334
section ..................................................................399
section type, restriction on....................................401
sector configuration of flash memory....................357
sector erase..........................................................362
sector erase operation status .......................366, 367
serial control register (SSR), bit function of ..........250
serial control register (SSR), configuration of.......250
serial input data register (SIDR) and serial output data
register (SODR), configuration of ...............252
serial mode register (SMR), bit function of ...........248
serial mode register (SMR), configuration of ........248
serial status register (SSR), bit function of ...........253
serial status register (SSR), configuration of ........253
shift instruction......................................................412
simulator debugger...............................................402
single conversion mode........................................276
single DRAM interface read timing chart ..............185
single DRAM interface write timing chart..............186
single DRAM interface timing chart ......................187
single PWM timer channel, block diagram of .......303
single/block transfer mode....................................335
sleep controller block diagram................................95
sleep mode, DMA transfer operation in ................340
sleep or stopped state, recovery from ....................28
sleep state, outline of..............................................90
sleep state, returning from......................................96
sleep state, transition to..........................................95
source oscillation at power-on, input of ..................27
special register .................................................33, 36
SSP ........................................................................37
standard branch (without delay) instruction..........415
standard branch macro instruction, 20-bit ............418
standard branch macro instruction, 32-bit ............420
standby control register (STCR), bit function of......78
standby control register (STCR), configuration of ..78
INDEX
431